Some of the CPU industry’s heaviest hitters—including Intel, AMD, Qualcomm, Arm, TSMC, and Samsung—are banding together to define a new standard for chiplet-based processor designs. Dubbed Universal Chiplet Interconnect Express (UCIe for short), the new standard seeks to define an open, interoperable standard for combining multiple silicon dies (or chiplets) into a single package.
Intel, AMD, and others are already designing or selling chiplet-based processors in some form—most of AMD’s Ryzen CPUs use chiplets, and Intel’s upcoming Sapphire Rapids Xeon processors will, too. But these chips all use different interconnects to enable communication between chiplets. The UCIe standard, if it succeeds, will replace those with a single standard, in theory making it much easier for smaller companies to take advantage of chiplet-based designs or for one company to include another company’s silicon in its own products.
Chiplet-based designs are advantageous when making large chips on cutting-edge manufacturing nodes partly because they cut down on the amount of silicon manufacturers need to throw out. If a manufacturing defect affects one CPU core, tossing (or binning) a single 8-core chiplet is a whole lot cheaper than having to toss a huge 16- or 32-core processor die. Chiplet designs also let you mix-and-match chips and manufacturing processes. You could, for example, use an older, cheaper process for your chipset and a newer, cutting-edge process for your processor cores and cache. Or you could put an AMD GPU on the same package as an Intel CPU.
As AnandTech reports, the UCIe standard will cover the physical and protocol layers of chiplet design. The standard will define how the chiplets need to be connected to each other and the protocol for facilitating communication between chiplets. But chip designers will be free to package those chiplets in whatever way they see fit, allowing the chiplets to talk to each other directly through the package substrate or using some kind of silicon-based bridge or other intermediary.
To accommodate these different physical packaging options, version 1.0 of UCIe defines two different performance levels. The “standard” package calls for 16 data lanes and as much as 25 mm of space between chiplets, while the “advanced” package uses 64 data lanes and allows just 2 mm of space.
The protocols underlying UCIe are PCI Express and the related Compute Express Link (CXL) standards, which are both mature and familiar to chipmakers. But companies that have already developed more advanced or specific protocols for inter-chiplet communication, like AMD and its Infinity Fabric, will be able to use those protocols while remaining UCIe-compliant. UCIe was primarily developed by Intel and then donated to the broader UCIe group to serve as the foundation for the new standard. But the group’s member companies “will begin work on the next generation of UCIe technology” together starting later this year.
If you want more technical details on the UCIe standard, you can find the white paper here.
Listing image by AMD